The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
In a high speed serial communication link, such as a 10 Gigabit (10 G) or 100 Gigabit (100 G) Ethernet connection, a transmitter transmits a data signal into a communication channel (channel). The data signal includes a sequence of symbols, each symbol carrying information from some number of bits, such as one, two, or more bits, or in some cases fractions of bits. The data signal may be an analog data signal.
The symbols are transmitted at a modulation rate expressed in baud, where one baud is one symbol per second. The duration of each symbol is known as the Unit Interval (UI).
In order to receive the data on the communication link, a receiver converts the analog data signal into a digital signal using an Analog to Digital Converter circuit (ADC). The ADC may perform one analog to digital conversion during each UI or may perform a plurality of analog to digital conversions during each UI.
At high sampling rates, a Time-Interleaved ADC (TI-ADC) may be used to perform the analog to digital conversions. A TI-ADC includes a plurality of ADCs that operate in parallel. In a TI-ADC performing one analog to digital conversion per sampling period with a duration of S nanoseconds and including N ADCs, that is, an “N-times TI-ADC,” the TI-ADC may operate using N sampling clocks each having a period of N·S nanoseconds and each lagging the previous sampling clock by S nanoseconds, each of the N sampling clocks controlling a respective one of the N ADCs. The output of the TI-ADC is a composition of the N ADCs of the TI-ADC. When all of the N ADCs operate identically, the composition of all N ADC outputs is equivalent to a single ADC performing sampling and conversion once every S nanoseconds.
That is, in the N-time TI-ADC, each of N ADCs samples the analog data signal once every N·S nanoseconds and then perform a conversion on the sampled signal: a first ADC samples the analog data signal at 0, N·S, 2N·S, . . . nanoseconds; a second ADC samples the analog data signal at S, (N+1)·S, (2N+1)·S, . . . nanoseconds; and so on; and an Nth ADC samples the analog data signal at (N−1)·S, (2N−1)·S, (3N−1)·S, . . . nanoseconds. Because each ADC of the TI-ADC performs sampling and conversion for only 1/N of the sampling periods, each ADC may operate at a substantially slower speed than an ADC capable of performing conversions at a rate corresponding to the sampling period.
The quality of the output of the TI-ADC depends on the individual ADCs of the TI-ADC operating with a high degree of uniformity. However, because of manufacturing and environmental variations, operational characteristics that affect uniformity of an ADC's operation may vary among the individual ADCs of the TI-ADC.